`timescale 1ns / 1ps
`define DLY #1
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date:    09:57:02 12/04/2017
// Design Name:
// Module Name:    pcie8311
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module pcie8311(
	input					clk,
	input					ads_n,
	input					blast_n,
	input			[31:2]	la,
	input					lhold,
	output	reg				lholda,
	input					lwr_n,
	inout			[31:0]	PXI_LD,
	output	reg      		ready_n,

    input           [31:0]  READ_DATA,
	output	reg		[31:0]	data_latch,
	output	reg				wren,
	output	reg				rden,
	output	reg		[31:0]	addr
);


assign PXI_LD = (ready_n) ? 32'bz : READ_DATA;

//总线占用请求及响应电路模块（始终响应请求）
always @(posedge clk) begin
    lholda  <= lhold;
end

reg[2:0] state;
localparam	IDLE        = 3'h0;
localparam	WAIT0       = 3'h1;
localparam	ADDR_LATCH  = 3'h2;
localparam	WAIT1       = 3'h3;
localparam	WAIT2       = 3'h4;
localparam	VALID       = 3'h5;
localparam	COMMU_END   = 3'h6;

always @(posedge clk) begin
    case (state)
        IDLE: begin
            if (!ads_n) begin
                state   <= WAIT0;
            end else begin
                state   <= IDLE;
            end
        end
        WAIT0: begin
            state   <= ADDR_LATCH;
        end
        ADDR_LATCH: begin
            if (wren == 1 && rden == 0) begin
                state   <= VALID;
            end else if (wren == 0 && rden == 1) begin
                state   <= WAIT1;
            end else begin
                state   <= ADDR_LATCH;
            end
        end
        WAIT1: begin
            state   <= WAIT2;
        end
        WAIT2: begin
            state   <= VALID;
        end
        VALID: begin
            state   <= COMMU_END;
        end
        COMMU_END: begin
            state   <= IDLE;
        end
        default: begin
            state   <= IDLE;
        end
    endcase
end


always @(posedge clk) begin
    case (state)
        IDLE: begin
            ready_n		<= `DLY 1;
			wren		<= `DLY 0;
			rden		<= `DLY 0;
        end
        WAIT0: begin
            wren		<= `DLY 0;
			rden		<= `DLY 0;
			ready_n		<= `DLY 1;
        end
        ADDR_LATCH: begin
            addr		<= `DLY la;
			data_latch	<= `DLY PXI_LD;
            if (lwr_n) begin
                wren	<= `DLY 1;
				rden	<= `DLY 0;
				ready_n	<= `DLY 0;
            end else begin
                wren	<= `DLY 0;
				rden	<= `DLY 1;
				ready_n	<= `DLY 1;
            end
        end
        WAIT1: begin
            ready_n		<= `DLY 1;
			addr		<= `DLY addr;
			data_latch	<= `DLY data_latch;
			wren		<= `DLY 0;
			rden		<= `DLY 0;
        end
        WAIT2: begin
            ready_n		<= `DLY 1;
			addr		<= `DLY addr;
			data_latch	<= `DLY data_latch;
			wren		<= `DLY 0;
			rden		<= `DLY 0;
        end
        VALID: begin
            ready_n		<= `DLY 0;
			addr		<= `DLY addr;
			data_latch	<= `DLY data_latch;
			wren		<= `DLY 0;
			rden		<= `DLY 0;
        end
        COMMU_END: begin
            ready_n		<= `DLY 1;
			addr		<= `DLY addr;
			data_latch	<= `DLY data_latch;
			wren		<= `DLY 0;
			rden		<= `DLY 0;
        end
        default: ;
    endcase
end


endmodule
